Modern integrated circuits, components and devices include data channels such as structures that transmit and/or receive data, and other structures that store and/or retrieve data from memory. Some of these structures are designed to protect the data by using parity bits for error detection or performing error correction code (ECC) detection and correction using ECC bits or another correction scheme. An ECC may be generated for a number of data bits to be protected that is sent or stored with the data bits to allow a retrieval (or receiving) end to detect whether an error has occurred in the data bits, and in some cases, to allow that error to be corrected.
In modern ECC memory structures, for example, use of a Hamming code has made possible single bit error correction (SEC) and double bit error detection (DED), also known as SECDED. The number of data bits to be protected dictates how many ECC bits are needed for SECDED protection, where the ECC bits contribute to the total number of bits used. For example, 6 (six) ECC bits may protect up to 26 bits of data, 7 (seven) ECC bits may protect up to 57 bits of data, and 8 (eight) ECC bits may protect up to 120 bits of data.
There has arisen the desire to add to data bits (e.g., in the number of metadata bits related to cache memory structures in one case), without modifying the design or manufacturing of parts of an integrated circuit chip capable of the storage or communication of those data bits. In these cases, however, adding to the number of bits stored in memory takes away from the number of ECC bits available for error protection, thus negatively impacting the ability to correct and detect errors. What is needed, therefore, is the ability to both increase the number of data bits for transmission or storage while not negatively impacting the ability to correct/detect errors.